1. Field of the Invention
The present invention relates generally to processors adopting a Very Long Instruction Word (VLIW) architecture executing consecutively or in parallel a plurality of instructions included in a single instruction word, referred to as VLIW processors, and particularly to VLIW processors accepting branching to an instruction executed during a consecutive execution.
2. Description of the Background Art
In recent years, there has been a demand for an enhanced processor performance in various fields such as multi-media processing, high-definition image processing. Devices manufactured by the current Large Scale Integration (LSI) fabrication technology, however, are limited in their operating speed. Accordingly VLIW processors have been noted and increasingly studied and developed.
A VLIW processor allows multiple operation instructions included in a single instruction word to be executed in a single cycle to enhance parallelism to provide an enhanced processor performance. It is known, however, that operations which cannot be executed in parallel cannot be encoded into a single instruction word and accordingly the instruction word has a No Operation (NOP) instruction inserted therein, resulting in a poor coding efficiency. To provide a technique to overcome this disadvantage, U.S. Pat. No. 5,761,470 discloses an invention.
In the data processor disclosed in U.S. Pat. No. 5,761,470, however, a branch target address indicated by a displacement of a branch instruction corresponds to a boundary of an instruction word and is thus constantly required to be the first operation instruction in the instruction word (an instruction prepared at a boundary of an instruction word). Thus an operation instruction immediately preceding a branch target and an operation instruction of the branch target cannot be encoded in a single instruction word and must thus be encoded in two instruction words with a NOP instruction buried between the two operation instructions. Thus the conventional data processor has a poor efficiency of instruction-code compression.
One object of the present invention is to provide a VLIW processor accepting branching to an operation instruction executed during a consecutive execution.
Another object of the present invention is to provide a VLIW processor capable of reducing the number of inserted no-operations to provide an enhanced efficiency of instruction-code compression.
Still another object of the present invention is to provide a VLIW processor capable of reducing a latency introduced when an exception or an interruption occurs.
Still another object of the present invention is to provide a VLIW processor capable of providing an enhanced program debug efficiency.
Still another object of the present invention is to provide a VLIW processor capable of reducing an instruction execution cycle to provide rapid processing.
The VLIW processor in an aspect of the present invention includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction word, and an execution unit using a result of decoding a plurality of operation instructions from the instruction decode unit to execute the plurality of operation instructions, wherein the execution unit includes a program counter control unit controlling a value of a program counter and providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during an consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced.
The program counter control unit providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during an consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced, allows branching to the operation instruction executed during the consecutive execution and can thus provide an enhanced efficiency of instruction-code compression.
The VLIW processor in another aspect of the present invention includes an instruction decode unit, a memory unit and an integer operation unit, wherein an instruction word includes a plurality of operation instruction fields, a branch target""s operation instruction designating field and a format field, the memory unit includes an operation instruction designating register receiving the branch target""s operation instruction designating field, the instruction decode unit includes a format field decoder receiving the format field, a plurality of instruction decoders receiving the plurality of operation instruction fields, respectively, and a plurality of output control units receiving a decode result from the format field decoder, a value of the operation instruction designating register and a decode result from each of the instruction decoders, and also connected to the memory unit or the integer operation unit.
The plurality of output control units receiving a decode result from the format field decoder, a value of the operation instruction designating register and a decode result from each of the instruction decoders, and also connected to the memory unit or the integer operation unit, allows branching to an operation instruction executed during a consecutive execution and can thus provide an enhanced efficiency of instruction-code compression.